1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory in which a layout area is reduced.
2. Description of the Related Art
In order to access a memory cell of a semiconductor memory, an address signal to the memory cell is externally supplied and is decoded by a decoder. As a result, a word line and a bit line corresponding to the decoded signal are activated. The decoder needs address signal lines and logic elements for the number of bits of the address signal.
FIG. 1 shows a conventional example of the decoder in a semiconductor memory. The decoder is described in Japanese Laid Open Patent Application (JP-A-Heisei 4-178027). As shown in FIG. 1, in the decoder, a 3-bit address signal is converted into an 8-bit decoded signal. That is, 6 wiring lines for the 3 bits a0, a1 and a2 of the address signal and these inverted bits are supplied to eight 3-input NAND circuits. Thus, the 8-bit decoded signals AA0, AA1, of . . . , AA7 are obtained. The NAND circuit contains 3 N-channel transistors.
Moreover, according to the above reference, in case that the memory is a semiconductor memory, a reset switching circuit must be connected with the NAND circuit.
FIG. 2 is a circuit diagram of the NAND circuit to which the reset switching circuit is connected. As shown in FIG. 2, the NAND circuit contains N-channel transistors TN1, TN2 and TN3, and the reset switching circuit contains P-channel transistors TP3, TP4 and TP5.
FIG. 3 shows a circuit when the above reset switching circuit is simplified. An inverted signal of an address transfer pulse signal ATD is used as a reset signal and is supplied to the reset switch circuits The number of wiring lines and the number of transistors are reduced.
However, with the development of a large capacity of a semiconductor memory, there is a problem in that a ratio of a decoder area and a wiring line area to the whole layout area in the semiconductor memory becomes large if the above conventional decoder is used.
In the above mentioned conventional example, when the number of address bits which are connected to the decoder is 3, 3 transistors are necessary for the 3-input NAND circuit, 2 transistor for the reset switching circuit and 2 transistors for the inverter. Therefore, seven transistors are necessary in the decoder. Thus, a large area is necessary for the layout of the decoder.
Also, for example, in a semiconductor memory using an 11-bit address signal, when first and second bits of the address signal are decoded and the remaining 9 bits of the address signal are decoded for every 3 bits, the number of wiring lines relating to a decoder is 28 (=4+3.times.8). In this case, the number of wiring lines can be slightly reduced by changing the decoding method. However, it is impossible to largely reduce the number of wiring lines. Therefore, when the number of bits of the address signal increases from 11, to 14 and then to 16, the number of wiring lines also increases with it, so that it is difficult to design the layout of the wiring lines.
Also, for the convenience of layout, a precharge control circuit PDL for generating a bit line precharge signal can not sometimes be arranged in the intersecting position of a sense amplifier SA column and a decoder row. In this case, as shown in FIG. 4, a precharge control circuit PDL is arranged in a peripheral portion 81. However, it is necessary that wiring lines of predecoded signals for all of address bits are arranged for the decoder row. Also, wiring lines for several bits of an address signal are required to be arranged in the peripheral portion 81 for the precharge control circuit PDL in addition to the wiring lines of the predecoded signals. That is, in case of the address signal of 11 bits, if a precharge signal is generated by use of 3 address bits, wiring lines for these 3 bits must be added to the layout. Therefore, the wiring line area further increases.
In conjunction with the above, a decoder circuit is described in Japanese Laid Open Patent application (JP-A-Showa 62-76824). In this reference, the decoder circuit is composed of a plurality of MOS transistors, a first MOS transistor, a second MOS transistor and an inverter circuit. The gates of the plurality of MOS transistors having a first channel type are supplied with different input signal. One off two ends of a current path of each MOS transistor is connected to an output terminal of a decoded signal and the other end is connected to a predetermined potential point in common to the MOS transistors. The first MOS transistor having a second channel type has a current path between a power supply potential and the output terminal and a gate supplied with a precharge control signal. The second MOS transistor having the second channel type is provided such that its current path is connected in parallel to that of the first MOS transistor. The inverter is connected at its input to the output terminal and at its output to the gate of the second MOS transistor.
Also, a semiconductor memory device is described in Japanese Laid Open Patent application (JP-A-Heisei 7-147087). In this reference, A bit line pair (BL, XBL), a precharging circuit (102), a switch circuit (103), a timing control circuit (106) and a sense amplifier (107) are provided for each of a plurality of memory cells (101) connected to a word line (WL) activated by a row decoder (104). The timing control circuit 106 outputs a word line control signal (WC) and a switch control signal (SC) such that the memory cell (101) and a sense amplifier 107 are rapidly disconnected at the time when the potentials of the bit line pair (BL, XBL) change to the degree that the sense amplifier (107) can operate, after the bit line pair (BL, XBL) has been precharged and the word line (WL) is activated. The inactivation of the word line (WL) is controlled by an OR gate (108) and an AND gate (105). Thus, the decrease of bit line potentials is suppressed such that power consumption at the precharging operation of the semiconductor memory can be reduced.
Also, "Super LSI Memory" by Kiyoo ITOH (published from BAIHUUKAN on Nov. 5, 1994) describes a basic circuit of a word driver. FIG. 2.54 shows a repetition unit of the word driver. A decoder is supplied with address signals Xj and Xk obtained by predecoding into 2 bits. The decoder is provided for 4 word lines. The word lines are divided into two groups and the decoder is common to the groups. One decoder is selected and one of the common word lines is selected by use of other two address bits. Thus, a pulse voltage is supplied to corresponding word lines of the groups.